object(WP_Post)#1995 (24) {
  ["ID"]=>
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  string(1) "1"
  ["post_date"]=>
  string(19) "2021-07-17 18:10:21"
  ["post_date_gmt"]=>
  string(19) "2021-07-17 10:10:21"
  ["post_content"]=>
  string(1530) "

We need to make these changes to qemu, to make our simulator workbench to capture all data we need, including all instruction disassemble lines and memory access records
1. git clone https://github.com/qemu/qemu.git
2. since latest qemu not work with xv6, so switch to v5.2.0 by git checkout tags/v5.2.0
3. modify accel/tcg/translate-all.c, infunction tb_gen_code, change this

    if (phys_pc == -1) {
        /* Generate a temporary TB with 1 insn in it */
        cflags &= ~CF_COUNT_MASK;
        cflags |= CF_NOCACHE | 1;
    }

To

    if (phys_pc == -1 || true) {
        /* Generate a temporary TB with 1 insn in it */
        cflags &= ~CF_COUNT_MASK;
        cflags |= CF_NOCACHE | 1;
    }

4. Edit target/riscv/cpu.c, add "tlb_flush(cs);" at the end of function "riscv_cpu_dump_state", to let use capture all memory r/w operations, we have to keep flushing the tlb, since TLB operations are not record in trace.
5. Compile Qemu

./configure --target-list=riscv64-softmmu --enable-plugins
make -j8
sudo make install
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Modify Qemu to support our RISC-V simulator dev 2021-07-17 18:10:21

We need to make these changes to qemu, to make our simulator workbench to capture all data we need, including all instruction disassemble lines and memory access records
1. git clone https://github.com/qemu/qemu.git
2. since latest qemu not work with xv6, so switch to v5.2.0 by git checkout tags/v5.2.0
3. modify accel/tcg/translate-all.c, infunction tb_gen_code, change this

    if (phys_pc == -1) {
        /* Generate a temporary TB with 1 insn in it */
        cflags &= ~CF_COUNT_MASK;
        cflags |= CF_NOCACHE | 1;
    }

To

    if (phys_pc == -1 || true) {
        /* Generate a temporary TB with 1 insn in it */
        cflags &= ~CF_COUNT_MASK;
        cflags |= CF_NOCACHE | 1;
    }

4. Edit target/riscv/cpu.c, add "tlb_flush(cs);" at the end of function "riscv_cpu_dump_state", to let use capture all memory r/w operations, we have to keep flushing the tlb, since TLB operations are not record in trace.
5. Compile Qemu

./configure --target-list=riscv64-softmmu --enable-plugins
make -j8
sudo make install
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"
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  string(53) "OUHK students finished their fyp about RISC-V with us"
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OUHK students finished their fyp about RISC-V with us 2021-07-01 00:10:17