Our rough development plan for the logic synthesizer. Erica will be the programmer. The study plan is solid but the dev plan is draft

Goal

1. Building the logic synthesizer is the final goal
2. Our ultimate goal is to output bitstream directly for ecp5 / gowin, then we know the complete process of logic synthesis

Study these

1. Logic synthesis book https://peter.quantr.hk/2023/01/good-book-on-logic-synthesis
2. HDL synthesis book https://peter.quantr.hk/2023/02/good-hdl-synthesis-book
3. IEEE Verilog specification 1364 https://www.eg.bucknell.edu/~csci320/2016-fall/wp-content/uploads/2015/08/verilog-std-1364-2005.pdf
4. IEEE Standard for Verilog Register Transfer Level Synthesis https://standards.ieee.org/ieee/1364.1/2053/

Software stack

1. Antlr as the parser and lexer
2. Verilog grammar using https://github.com/antlr/grammars-v4/tree/master/verilog
3. Java + Netbeans IDE
4. Maven as build system

Stage

1. Test the Verilog Antlr grammar is strong enough to parse big Verilog file (done)
2. Define the IR data structure to store converted logic gate information
3. Create parse to read HDL and convert into IR data structure