Verilog Compiler

Goal

A verilog macro preprocessor, we are designing our own marco to support our RISC-V cpu development

Macro

Auto wire two modules, need to base on the wire name standard

@{connect(moduleA, module B)}

Generate code to dump pin 1 information into our own trace format file

<@{dump(moduleA.pin1)}>

CLI Usage

usage: java -jar verilog-compiler-xx.jar [OPTION] <input file>
 -h,--help                                help
 -j,--json <.v file>                      verilog to json
 -m,--macro <.v file>                     process macro in verilog file
 -o,--macro <output file>
 -p,--json <folder, top module .v file>   parse topmodule and return json
 -t <.v file or folder>                   compile verilog file,
                                          post-process it for our debugger
 -tvh <verilog heading statements>        work with -t option to
                                          post-process and inject verilog
                                          statement
 -tvs <verilog statements>                work with -t option to
                                          post-process and inject verilog
                                          statement
 -v,--version                             display version
Examples:
    1. java -jar target/verilog-compiler-2.0.jar -j ex.v
    1. java -jar target/verilog-compiler-2.0.jar -p ex.v
    1. java -jar target/verilog-compiler-2.0.jar -t src -tvh '' -o src-output

java -jar verilogcompiler-xx.jar -j quantr_i.v

Result:

[ {
  "name" : "quantr_i",
  "inputs" : [ {
    "direction" : "input",
    "name" : "clk"
  }, {
    "direction" : "input",
    "name" : "rst"
  } ],
  "outputs" : [ {
    "direction" : "output",
    "range" : "[`MXLEN]",
    "name" : "pc"
  } ]
} ]

Source code explain

Verilog preprocess is complex, here is the flow

  1. run the verilog by -t command
  2. VerilogHelper.preProcess()
  3. String sourceContent = VerilogHelper.getContentReplacedWithMacro(1, content, VerilogHelper.scanMacroDefinitions(file, file.getParentFile()), ps);
  4. ps.fatternMacroListing()
Peter
Tsz Chung Law
Derek Tang
Cheng Darren
Lok Szeto
Ken Lam
michellechw
Ronald Park
Developer performance
Status Job Pipeline Stage Commit Msg Timing
success #3963746836 main d04ef3fa
verilog-compiler
#811542641 Peter deploy
Add LICENSE
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1 year, 1 month
success #3963746834 main d04ef3fa
verilog-compiler
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Add LICENSE
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verilog-compiler
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making the debugger hook to file quantr.profiling
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making the debugger hook to file quantr.profiling
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#578921943 Peter build
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success #2670340989 main 092efa17
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#578491452 Peter deploy
Proecess for $display now working !!!
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#578491452 Peter build
Proecess for $display now working !!!
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$display placed to correct position in MarcoListing now
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#578128727 Peter build
$display placed to correct position in MarcoListing now
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done, can parse the whole quantr-i/src, verilator compile ok
0:12
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verilog-compiler
#576203143 Peter build
done, can parse the whole quantr-i/src, verilator compile ok
0:8
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success #2645330819 main fe2eaebf
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Merge origin/main into main
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Merge origin/main into main
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