Our rough development plan for the logic synthesizer. Erica will be the programmer. The study plan is solid but the dev plan is draft
Goal
- Building the logic synthesizer is the final goal
- Our ultimate goal is to output bitstream directly for ecp5 / gowin, then we know the complete process of logic synthesis
Study these
- Logic synthesis book https://peter.quantr.hk/2023/01/good-book-on-logic-synthesis
- HDL synthesis book https://peter.quantr.hk/2023/02/good-hdl-synthesis-book
- IEEE Verilog specification 1364 https://www.eg.bucknell.edu/~csci320/2016-fall/wp-content/uploads/2015/08/verilog-std-1364-2005.pdf
- IEEE Standard for Verilog Register Transfer Level Synthesis https://standards.ieee.org/ieee/1364.1/2053/
Software stack
- Antlr as the parser and lexer
- Verilog grammar using https://github.com/antlr/grammars-v4/tree/master/verilog
- Java + Netbeans IDE
- Maven as build system
Stage
- Test the Verilog Antlr grammar is strong enough to parse big Verilog file (done)
- Define the IR data structure to store converted logic gate information
- Create parse to read HDL and convert into IR data structure
