We are going to start our breadboard RISC-V project. We build a simple RISC-V with students to fulfill the below requirements. The breadboard CPU is simple, but we will be in full stack, code the testing program in GCC, debug via GDB with our own jtag and by openocd.

Requirements:

1. A controllable program counter. We can set its speed and pause it at any time manually
2. Support some basic instructions such as below
3. Provide LED to indicate the status and register values on board
4. Data bus & instruction bus
5. 3 Stage pipeline and visualize it
6. We use STM32 to build the USB tag and plug to our breadboard RISC-V, write openocd driver and able to dump out registers and single step via GDB

Remark 1:

Outside the RISC-V we still need some components such as a programmable clock generator, we do all that by ATtiny85 and flash it via this device

Remark 2:

For the memory rather than using gates, we use dip memory such as 24AA32AF and this device and flash the EEPROM memory

Bill Of Material

	Thing	Qty	Price
	Digital Design and Computer Architecture: RISC-V Edition	4	$350
	Breadboard	60	$180
	We need some OLED (don’t know how many, just buy them all) 0.96 inch x 20 + 1.3 inch x 20	40	$600
	LED	200	$80
	8-segments LED	100	$300
	USB Power Supply	3	$60
	Button x 50 for each student	3	$80
	Cable x 300 for each student	3	$50
	We need some gates but I don’t know which one, so buy them all	3	$800
	Switch	3	$80
	STM32 board and JTag to offload some logic outside RISC-V	3	$100
	Tester	3	$300
	Logic Analyzer	3	$80
	Ben Eater Complete 8-bit breadboard computer kit bundle	3	$7020
	Multimeter	3	$800
		Total =	$10880

We will have another hobby project with Dim Sum Labs. Our ultimate goal is to design our own STM32 board. Philip Paeps is one of the guy running Dim Sum Labs and he is a low-level guy, I and him have nearly the same interests. Philip is a FreeBSD committer contributing mainly to the kernel and a member of the FreeBSD security team.

Our plan:

1. We design and make our own STM32 board
2. We use this to put the STM32 chip into the breadboard and make it work first
3. We use kicad as the tool, there are some tutorials we just follow
4. For Jtag, we should support ST-Link
5. I got STM32 board and they provide the schema, maybe we just follow first. But we have to understand the meaning of every piece and every number in it.
6. We produce our PCB board in here. It got PCB assembly service, lets get familiar with it.
7. If we are not dead, our next stop would be design our own FPGA board just like the icesugar-pro and make sure the open source toolchain can run on it.

Go to jump into logic simulator development, now calculating the level of each gate

“Qemu Log Panel” is the tailor-made software to

1. Convert qemu.log into H2 database
2. Provide a GUI to diff the H2 database from xv6-riscv to the H2 database generated by our simulator

Step to run it

Record xf6-riscv

1. Clone xv6
2. Modify the Makefile
3. Run “make qemu”, then you got qemu.log
4. Run “make h2”, then it converts qemu.log into h2 database “database.mv.db”

Record our simulator

1. Run our simulator in netbeans with “-h2” option
2. Then you got “dump.mv.db”

Run the GUI

1. run qemu-log-panel, point to those two H2 database files

We support gifted talent, including technical training, and join our open-source projects to grant coding experience. Teen has talent in coding, they code well on logic. But the modern coding world is complex, lots of frameworks, libraries, hidden rules, and styles. They need experienced people to provide them with hand-to-hand training, and level up their skills. This will shorten the time to conquer these skill sets, rather than spending decades for self-learning. We have three streams

CPU stream – Join our CPU team to develop a microprocessor. Our goal is to fabricate a CPU with all basic features such as cache, branch prediction, jtag & trace capability, I/O, interrupt controller, and others. Students will learn a new programming paradigm: HDL, understand how your code converts to logic, and how all fundamental stuff work. CPU is the heart of the computer and the ground of logic execution. If you are interest into how the computer executes your code, join this.

Operating system stream – To create an OS for x86 and RISC-V, support all modern OS features such as multitasking, libc/libc++, driver model, locking, and others… OS works like the human brain, controlling all peripheral devices just like our brain controls our hands and legs. OS is the big brother of all software, it decide what to run and how all other programs behave.

Web team – We are not just doing website programming, we are building fundamental blocks to support websites. Many projects, such as web server, database, high-availability layer, logging engine, CMS, and others. We put effort into understanding how every piece works by building our own.

If you have spare time, join us

We are researching the http protocol and building our own http server. This guide build nginx and test it out.

Build php

wget https://www.php.net/distributions/php-8.2.3.tar.xz
tar xvf php-8.2.3.tar.xz
cd php-8.2.3
Mac: ./configure --enable-fpm --prefix=/Users/peter/Downloads/my-php --with-iconv=$(brew --prefix libiconv) --with-mysqli
Linux: ./configure --enable-fpm --prefix=$HOME/Downloads/my-php --with-mysqli

If you in WSL, comment out "#define HAVE_LQ_TCP_INFO 1" from "main/php_config.h"

make -j
make install
cd ..

Build nginx

wget https://nginx.org/download/nginx-1.23.2.tar.gz
tar zxvf nginx-1.23.2.tar.gz
cd nginx-1.23.2
./configure --prefix=$HOME/Downloads/my-nginx
make -j
make install

Make nginx works with php

cd $HOME/Downloads/my-php/etc
cp php-fpm.conf.default php-fpm.conf
cd $HOME/Downloads/my-php/etc/php-fpm.d
cp www.conf.default www.conf
edit www.conf , change to "listen = 127.0.0.1:9876"
make sure "user = peter" and "group = peter". Remark : "group = peter" is for linux only
create index.php in $HOME/Downloads/my-nginx/html
cd $HOME/Downloads/my-php/sbin
sudo ./php-fpm

configure nginx

cd $HOME/Downloads/my-nginx/conf
edit nginx.conf

2. sudo ../sbin/nginx

To stop php-fpm and nginx:
sudo killall -9 nginx
sudo killall -9 php-fpm

Browse to http://localhost

Wireshark

Install wireshark, remember install ChmodBPF. Open loopback, then you see how nginx talk to php-fpm by port 9876

To enable FCGI, make sure FCGI is enabled by menu “analyze” -> “Enabled Protocols”:

Set the port to 9876, go to “Preference” – > “Protocols” -> “FCGI”, set the port to 9876:

Then filter the protocol by “fcgi”, you can see the captured packet matched with our code

We are researching the http protocol and building our own http server. This guide build apache and test it out.

wget https://dlcdn.apache.org/httpd/httpd-2.4.56.tar.bz2
tar jxvf httpd-2.4.56.tar.bz2
cd httpd-2.4.56/

sudo apt-get install apache2-utils libapr1 libapr1-dev libaprutil1-dev -y
./configure --enable-cgi --prefix=/home/peter/Download/my-httpd
make -j
make install

Then you have this

Run the apache with CGI connects to PHP

1. edit conf/httpd.conf , change “Listen 80” to “Listen 8765”
2. run bin/httpd

We failed to apply ESS from ITF for 1.6M HKD funding. We face the truth, hong kong is not the place to develop foundation open-source software & hardware. We close the team in hk today and move to another country.

Our rough development plan for the logic synthesizer. Erica will be the programmer. The study plan is solid but the dev plan is draft

Goal

1. Building the logic synthesizer is the final goal
2. Our ultimate goal is to output bitstream directly for ecp5 / gowin, then we know the complete process of logic synthesis

Study these

1. Logic synthesis book https://peter.quantr.hk/2023/01/good-book-on-logic-synthesis
2. HDL synthesis book https://peter.quantr.hk/2023/02/good-hdl-synthesis-book
3. IEEE Verilog specification 1364 https://www.eg.bucknell.edu/~csci320/2016-fall/wp-content/uploads/2015/08/verilog-std-1364-2005.pdf
4. IEEE Standard for Verilog Register Transfer Level Synthesis https://standards.ieee.org/ieee/1364.1/2053/

Software stack

1. Antlr as the parser and lexer
2. Verilog grammar using https://github.com/antlr/grammars-v4/tree/master/verilog
3. Java + Netbeans IDE
4. Maven as build system

Stage

1. Test the Verilog Antlr grammar is strong enough to parse big Verilog file (done)
2. Define the IR data structure to store converted logic gate information
3. Create parse to read HDL and convert into IR data structure