Initially, we were thinking of synthesizing our logic into FPGA, but most of the vendors don’t open their bitstream format, and hacking takes a huge amount of time. Now we have changed a new way: we synthesize our logic into PLD (programmable logic device), especially for CPLD or PAL.
Now we need a logic compiler, converting the diagram data structure which outputs from Quantr-Logic to boolean algebra, and compiles it into PLD format, which can be sent to the programmer to burn the logic.
The principle is to generate two h2 database file, one from executing qemu, one from executing riscv-simulator
- Go to /Users/peter/workspace/riscv-simulator/src/test/resources/hk/quantr/riscv_simulator/elf/timer
- make run , then you have cpu.log
- run “java -jar ~/workspace/qemu-log-panel/target/qemu-log-panel-1.0-jar-with-dependencies.jar -f cpu.log -t” to convert cpu.log to database.mv.db, which is the h2 database file
- Setup riscv-simulator as
5. run it, then you got the “dump.mv.db” in riscv-simulator folder
6. Now you can run the qemu-log-panel
Then you see this
This year MUHK FYP, join if you are MUHK student. These are our past project:
Gate-by-gate simulation is easy to implement, so our first stage is to implement the whole skeleton, including all components, the plugin engine, and the simulation engine. It has an obvious weak point: slow. We are now seeking a way to simulate a billion gates. We put our progress here. Here is our first attempt:
- We split the truth table and use RAM to direct output the result. Then the simulate no need to depend on the level of gate, it works much faster in most combinational circuits.
- We need to split the combinational circuit into piece and each piece work in similar duration, otherwise multithreading result will not be good, since some circuits take long time and some take short time to complete
- We need to think of offloading the simulation in GPU or FPGA. FPGA will work faster but the programming model is much harder and lack of cross-platform ability
- Trying the Tornardo VM to offload some java to CUDA
We are going to start our breadboard RISC-V project. We build a simple RISC-V with students to fulfill the below requirements. The breadboard CPU is simple, but we will be in full stack, code the testing program in GCC, debug via GDB with our own jtag and by openocd.
- A controllable program counter. We can set its speed and pause it at any time manually
- Support some basic instructions such as below
- Provide LED to indicate the status and register values on board
- Data bus & instruction bus
- 3 Stage pipeline and visualize it
- We use STM32 to build the USB tag and plug to our breadboard RISC-V, write openocd driver and able to dump out registers and single step via GDB
Outside the RISC-V we still need some components such as a programmable clock generator, we do all that by ATtiny85 and flash it via this device
Bill Of Material
We will have another hobby project with Dim Sum Labs. Our ultimate goal is to design our own STM32 board. Philip Paeps is one of the guy running Dim Sum Labs and he is a low-level guy, I and him have nearly the same interests. Philip is a FreeBSD committer contributing mainly to the kernel and a member of the FreeBSD security team.
- We design and make our own STM32 board
- We use this to put the STM32 chip into the breadboard and make it work first
- We use kicad as the tool, there are some tutorials we just follow
- For Jtag, we should support ST-Link
- I got STM32 board and they provide the schema, maybe we just follow first. But we have to understand the meaning of every piece and every number in it.
- We produce our PCB board in here. It got PCB assembly service, lets get familiar with it.
- If we are not dead, our next stop would be design our own FPGA board just like the icesugar-pro and make sure the open source toolchain can run on it.
Go to jump into logic simulator development, now calculating the level of each gate
“Qemu Log Panel” is the tailor-made software to
- Convert qemu.log into H2 database
- Provide a GUI to diff the H2 database from xv6-riscv to the H2 database generated by our simulator
Step to run it
- Clone xv6
- Modify the Makefile
- Run “make qemu”, then you got qemu.log
- Run “make h2”, then it converts qemu.log into h2 database “database.mv.db”
Record our simulator
- Run our simulator in netbeans with “-h2” option
- Then you got “dump.mv.db”
Run the GUI
- run qemu-log-panel, point to those two H2 database files